The distribution of television signals has increasingly become based on digital methods and digitally encoded forms of video and audio signals. At the same time, higher resolution (high definition TV) has become available in the market place, commensurate with larger and higher definition displays. To meet the requirement of interconnecting such high definition displays with digital signal sources such as Digital Versatile Disc (DVD) players and receivers/decoders for digital satellite and digital cable distribution of video material, a digital interface standard has evolved, known as the High-Definition Multimedia Interface (HDMI). A detailed specification for HDMI can be obtained from the “hdmi.org” website. The HDMI specification currently available and used in this application is HDMI specification version 1.3 dated Jun. 22, 2006, which is incorporated herein by reference. This HDMI standard can be employed for connecting digital video sources to digital video sinks over a cable that carries a number of digital signals and a clock signal.
The inherent characteristics and manufacturing imperfections of high-speed differential signaling cables such as may be used to carry HDMI signals have an adverse effect on the high-speed signals carried by the cable.
For example, any cable has a limited bandwidth and therefore acts as a low pass filter. The bandwidth of the cable is related to its length, the longer the cable the greater the filtering effect and the lower its bandwidth. As a result, high-frequency signals passing through the cable are attenuated, and their edges become less sharp. This leads to an increased risk of misinterpreting the received data at the receiver end of the cable, especially for long cables and high-speed data.
Previously filed patent applications of the applicant, all of which are incorporated herein by reference, 11/826,713 “A High-Speed Cable With Embedded Power Control', Ser. No. 11/826,716 “A Programmable High-Speed Cable With Boost Device”, Ser. No. 11/826,710 “A Programmable High-Speed Cable With Printed Circuit Board And Boost Device”, Ser. No. 11/826,711 “A Programmable Cable With Deskew And Performance Analysis Circuits”, and Ser. No. 11,826,712 “System And Method For Calibrating A High-Speed Cable”, all of which were filed on Jul. 18, 2008, have described an HDMI cable that includes a boost device.
FIG. 1 shows an HDMI system 10 including an improved HDMI cable 20 of the prior art. The HDMI system 10 includes an HDMI transmitter Tx (HDMI Source Device), an HDMI receiver Rx (HDMI Sink Device), and the improved HDMI cable 20 connecting the Tx to the Rx.
The improved HDMI cable 20 comprises an embedded boost device 30 and a basic (passive) HDMI cable 40. The boost device 30 is located near the end of the improved HDMI cable 20 closest to the HDMI receiver Rx. The improved HDMI cable 20 may be used to connect a DVD player to a Television Screen for example, or in general connect any HDMI Source Device to an HDMI Sink Device.
FIG. 2 shows a block diagram of circuits that are included in the boost device 30 of the HDMI system 10 of FIG. 1 of the prior art. The boost device 30 includes a number of channel boost circuits 100, and a parameter memory 102. Typically, the boost device 30 includes four (4) channel boost circuits 100, each to boost the signal of one of the TMDS Channel 0, the TMDS Channel 1, the TMDS Channel 2, and the Clock Channel. These four channels are high speed digital channels as described in the HDMI specification.
Each channel boost circuit 100 includes an HDMI Input Circuit 106 and an HDMI Output Circuit 108. Each channel boost circuit 100 may further include a Differential (intra-pair) Deskew Circuit 110 for adjusting an existing time skew of the two polarities of a differential data signal propagating through the basic HDMI cable 40 and an Equalizer Circuit 112 to compensate for the limited bandwidth characteristics of the basic HDMI cable 40. Each channel boost circuit thus provides a transfer function from the respective HDMI Input to the corresponding HDMI Output with characteristics designed to compensate for the degradation of the corresponding differential pair in basic cable 40.
The improved HDMI cable 20 comprising four boost circuits may be manufactured with any of a number of different lengths of the basic (passive) HDMI cable 40. To compensate for the differential skew and the frequency response of each individual cable, methods have been proposed in the above mentioned previous patent application Ser. No. 11/826,712 “System And Method For Calibrating A High-Sped Cable” for calibrating the Differential Deskew Circuit 110 and the Equalizer Circuit 112 through digital parameters stored in the parameter memory 102. The Parameter Memory 102 may be loaded with parameter values at the time of manufacture of the improved HDMI cable 20.
Three alternative methods have been proposed for calibrating the parameters: a Real Time Calibration method; a Frequency Domain Calibration method; and a Time Domain Calibration method. Because the physical cable is fairly stable, it is not necessary to dynamically adjust these parameters in the field, once they have been set originally, although the Real Time Calibration method could certainly be adapted to perform this.
The Frequency Domain and Time Domain Calibration methods require expensive external test equipment while the Real Time Calibration method additionally relies on an external HDMI data generator and a sophisticated performance analysis circuit built into the boost device 30.
FIG. 3 shows a generic test set up 200 for Frequency Domain and Time Domain Calibration methods of the prior art. The generic test set up 200 includes the improved HDMI Cable 20 (see FIG. 1), a PC 202, and a test equipment 204 that is either a VNA (Vector Network Analyzer) or a TDR (Time Domain Reflectometer). The PC 202 is attached to the control bus (SDA+SCL) of the basic HDMI Cable 40. The test equipment 204 is connected to the differential channels at both ends of the cable, that is the four differential channel inputs (8 wires) 208 and the four differential channel outputs (8 wires) 210 that are carrying the boosted signal.
The test equipment 204 is controlled by the PC 202 over a standard PC-interface 206 to send stimulus signals into the cable inputs (208) and to receive measurement results from the cable outputs (210). The results are passed back to the PC 202 over the standard PC-interface 206 for evaluation.
It is possible with the test equipment 204 being either a VNA or a TDR to obtain both frequency attenuation and delay characteristics of the cable, although well-known mathematical transformations are required to convert between the frequency and time domain results obtained with the VNA or the TDR respectively.
FIG. 4 shows a Real Time Configuration 300 used in a Real Time Cable Calibration method of the prior art. The Real Time Configuration 300 includes a Real Time Test Equipment 302 and the improved HDMI cable 20 of FIG. 1, which however includes an expanded boost device 304. The expanded boost device 304 includes the boost device 30 (FIG. 2) and additional circuitry for analyzing the boosted signal (210) and providing access to the control bus (SDA+SCL).
The Real Time Test Equipment 302 includes a +5V Supply to supply power to the cable; a Data Pattern Generator for generating HDMI-conforming differential data and clock signals to feed into the differential channel inputs (208), and a Control Computer (PC) to control the data patterns to be output by the Data Pattern Generator, and to communicate with the expanded boost device 304 in the cable over the control bus (SDA+SDL). A termination device “Term” that comprises a set of typical differential termination circuits is connected to the differential channel outputs 210.
To calibrate the cable (each cable is individually calibrated at production) the Real Time Calibration method may include the following steps:                a control program in the PC instructs the Data Pattern Generator to send HDMI data patterns into the differential channel inputs 208 of the cable;        the control program in the PC uses the control bus (SDA+SDL) to send deskew and equalization parameters to the expanded boost device 304;        the expanded boost device 304 performs the deskew and equalization steps as determined by the set parameters;        the expanded boost device 304 analyzes the quality of the deskewed and equalized signal;        the expanded boost device 304 reports the quality result to the PC over the control bus (SDA +SDL);        the preceding steps are repeated for each differential channel and with different parameters;        the best settings are determined and permanently set into the parameter memory 102 within the boost device 30.        
FIG. 5 shows a simplified block diagram of the expanded boost device 304 of the prior art, including the boost device 30, a Control Interface 306, and a performance analysis circuit 308.
Only a representative one of the four channel boost circuits 100 is shown in the FIG. 5, it being understood that each of the three differential TMDS channels and the differential clock channel are processed by a respective channel boost circuits 100.
The Control Interface 306 communicates with the Real Time Test Equipment 302 of FIG. 4 over the control bus SDA+SCL, and with the parameter memory 102 (in the boost device 30) over a parameter setup link 310.
The performance analysis circuit 308 is only active (powered up under control of the Control Interface 306) when the expanded boost device 304 is being calibrated.
The performance analysis circuit 308 includes a Differential-to-Single-Ended block 312, a Linear Phase Compensator 314, an Oversampling and Reclocking block 316, and a Training Function block 318. An output of the Training Function block 318 is connected to an input of the Control Interface 306 over a control link 320. Two optional outputs (parameter links 322) of the Training Function block 318 are connected to deskew and equalization parameter inputs 324 and 326 of the channel boost circuit 100, bypassing the Parameter Memory 102.
Not shown in FIG. 5 is a conventional clock recovery circuit which recovers the clock from any of the differential channels, and generates a multiphase clock signal (clock phases PH0 to PH23). The generation of the multiphase clock signal may be accomplished with a phase locked loop using any of a number of known techniques to generate multiple phases of a clock.
When each of the four channel boost circuits 100 is to be calibrated by the Real Time Cable Calibration method, its “boosted signal” pair 124 is tapped and connected to the performance analysis circuit 308.
Note that a single common performance analysis circuit 308 may be shared for calibrating the four channel boost circuits 100 sequentially. Alternatively, a plurality of performance analysis circuits 308 may be included in the expanded boost device 304 which would allow the channel boost circuits 100 to be calibrated in parallel.
In the performance analysis circuit 308 the “boosted signal” pair 124 is connected to the Differential-to-Single-Ended block 312 which converts the boosted signal 124 into a single-ended signal 328 that is input to the Linear Phase Compensator 314 which also receives the PHO phase of the multiphase clock signal, and produces as output a phase aligned signal 330.
The Oversampling and Reclocking block 316 receives the phase aligned signal 330 as well as all 24 phases (PH0 to PH23) of the multiphase clock signal, to generate a 24-sample digital samples signal 332 which is then input to the Training Function block 318.
After being converted to the single-ended signal 328 in the Differential-to-Single-Ended block 312, the data is ready to be sampled (converted into a digital signal). To define the phase relationship between the on-board clock (PHO of the multi-phase clock) and the data (the single ended signal 328), an Analog Phase detector (within the Linear Phase Compensator 314) is used. The frequency of the data and the recovered clock are equivalent because the timings in both are derived from the same source, that is, the transmitted clock, so there is no need for frequency adjustment. The Linear Phase Compensator 314 may be based on a scheme described in the paper entitled “A 10-Gb/s Clock Recovery Circuit with Linear Phase Detector and Coupled Two-stage Ring Oscillator” by Afshin Rezayee and Ken Martin. This paper, which is incorporated herein by reference, was published at the European Solid State Circuits Conference (SSCIRC) in Florence, Italy in the year 2002, pp. 419-422.
The phase aligned (data) signal 330 is a rail-to-rail analog signal that may still contain Inter Symbol Interference (ISI), distortion, noise, and other impairments. In the Oversampling and Reclocking block 316, this signal is effectively sampled at a rate 12 times the clock rate of the signal, i.e. during each bit period the data signal is sampled at 12 evenly spaced intervals, to generate 12 digital samples. Because of the high speed of the signal (typically 1.65 Gbs) it is not practical to actually sample the signal with a 12-times higher clock signal. Instead, the same effect is achieved by sampling the signal with 12 evenly spaced phases of the clock signal, each clock phase generating a digital sample, thus 12 samples representing one data bit. As described in the above cited patent application Ser. Nos. 11/826,713 and 11/826,716, 24 clock phases (PH0 to PH23 of the multiphase clock signal) are used to capture not only one data bit in 12 sampling phases, but also the trailing half of the previous data bit in 6 sampling phases and the leading half of the next data bit in another 6 sampling phases. Conventional digital register logic and pipelining is used to thus look into the “future”.
Thus, the Oversampling and Reclocking block 316 generates 24 samples (a “24-sample word”) at the bit-clock rate, by outputting the 24-sample digital samples signal 332.
FIG. 6 illustrates with a diagram 400 an example of oversampling in the Oversampling and Reclocking block 316 of FIG. 5. The diagram 400 in FIG. 6 shows an exemplary waveform 402, a delayed waveform 404, a set of sampling clocks 406, a 24-sample word 408, and a scale indicating a bit-period and previous and next bits.
The exemplary waveform 402 represents an example of the single ended signal 328 (FIG. 5) before phase alignment. Note that the signal appears to be a “1” bit with some distortion (noise or ISI) near the one-zero transition, and it is not aligned with the indicated bit-period. The delayed waveform 404 represents the corresponding phase aligned signal 330 after delay through the Linear Phase Compensator 314. Note that the signal is now approximately aligned with the indicated bit-period, but still includes the distortion. This signal is sampled with the 24 phases of the multiphase clock (PH0 to PH23) as indicated by the set of sampling clocks 406 in the Oversampling and Reclocking block 316, resulting in the 24-sample word 408. The 24-sample word 408 includes six samples (000000) from the previous bit period, twelve samples (111111111100) from the Bit-period and another six samples (000000) from the next bit period.
The 24-sample word 408 is output by the Oversampling and Reclocking block 316 as the 24-sample digital samples signal 332 to the Training Function 318.
The Training Function 318 (FIG. 5) may provide feedback to the Real Time Test Equipment 302 (FIG. 4) by evaluating the 24-sample digital samples signal 332, which is a stream of 24-sample words such as illustrated in the 24-sample word 408 of FIG. 6. In this way, the Real Time Test Equipment 302 may be able to tune the adjustable parameters of the channel boost circuit 100 that is presently being calibrated.
In another approach the Training Function 318 may systematically go through each of the possible permutations of settings of these parameters; observe and measure the quality of the preprocessed signal (the single ended signal 328 that is oversampled as the 24-sample digital samples signal 332) to obtain a quality measure in the form of a “Quality Number”; and retain the settings that yield the best Quality Number in the parameter memory 102 (FIG. 5).
Although the Real Time Calibration method could be conducted under step by step control through the PC, it may be advantageous to allow the Training Function 318 to bypass the Parameter Memory 102 and perform repetitive steps of setting trial values of the parameters (126 and 128) autonomously, and only report the final result for each channel to the PC which may then load the “best” settings into the Parameter Memory 102.
Alternatively, the PC may be used only to start the Real Time Calibration, the final results (the “best setting”) being autonomously loaded into the parameter memory without intervention by the PC.
In the calibration methods of the prior art described above, access to the boost device for controlling the calibration process that includes setting parameters in the boost device, is provided over the control bus comprising “Serial Data” (SDA) and “Serial Clock” (SCL), typically from a control computer (PC). Furthermore, test equipment in the form of a Vector Network Analyzer, a Time Domain Reflectometer, or a high-speed data pattern generator is needed to stimulate the differential high-speed HDMI channels for the calibration. And in the Real Time Calibration method, a complex high-speed oversampling circuit and quality evaluation circuit is built into the expanded boost device 304.
A more economical calibration method for boosted HDMI cables is required in terms of calibration equipment cost, and time to set up the calibration process.